`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 			Arizona State University
// Engineer: 			Joe Boeding
// 						Taylor Wood
//
// Create Date:    	14:44:55 04/01/2013 
// Design Name: 		button_pulse_generator
// Module Name:    	button_pulse_generator 
// Project Name: 		LAB #2
// Target Devices: 	Xilinx Spartan6 XC6LX16-CS324
// Tool versions: 	Xilinx ISE 14.2
// Description: 		
//		This is just a wrapper for the hysterisis module to conform with the
//		block diagram convention.  This is a wrapper, because the switch is 
//    already latching, and switch noise needs eliminated
//
// Dependencies: 		button_handler.v
//
// Revision: 		
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module switch_latcher # (parameter SIGHYS_ON = 100000, SIGHYS_OFF = 240000)(
    /* Inputs  */ input i_switch, i_clk, i_resetb,
    /* Outputs */ output o_latched_data
    );
	 
	 sig_hys #(
		.TURN_ON_CLOCK_COUNT(SIGHYS_ON),	   // measured lab values @ 100mHz
		.TURN_OFF_CLOCK_COUNT(SIGHYS_OFF)	// measured lab values @ 100mHz
	 ) sh (
	 .dir_sig(i_switch),					
    .clk(i_clk),
    .reset_b(i_resetb),
    .fil_sig(o_latched_data)
	 );
	 
endmodule
